RTS output and Visa write not in sequence

I am asserting RTS, writing and unasserting RTS, as shown below. unassert/assert state doesn't matter, RTS write is happening out of sequence.

 However on the scope I can see write starts, then RTS is asserted and quickly unasserted before write completes. I tried synch and asynch write and just put a sequence frame to no avail. VI is attached. Please help. Thanks.