Hi everyone,
I have been using the Balanced I/O Personality (http://www.ni.com/example/5961/en/) to generate and acquire analog signals. However, I am finding that it doesn't quite fit the requirements of my application.
I would like to acquire and generate data in a synchronized manner. I recently completed the online FPGA course, but I am still left with some questions, regarding how to modify this particular code to fit my requirements.
I would like to run acquisition and output loops at the same clock rate. For that, I understand that I need to use the same loop timer ticks for the AI and AO loops, which will be hard-coded into the FPGA. I also understand that the AI and AO while loops only start running if the "AI Enable" and "AO Enable" booleans are set to true. Should I only use one boolean which enables both at the same time in the FPGA VI?
Also, most of my confusion lies in the way the Host VI works. I would like to output and acquire a finite number of samples, starting at the same time. I am not sure which functions of the code should be synchronized. Please find attached an image containing the two original codes for AO and AI and my suggested changes to make them run simultaneously. I would really appreciate it if someone could suggest whether my proposed changes make sense and point me in the right direction.
The FPGA course brought to my attention the use of occurences to synchronize tasks - should I be using them for this code?
Thanks in advance, and looking forward to your replies.