Hi,
I recently bought the cRIO-9075 but in order for me to design the software-firmware architecture I need to get same answers for the following questions (I'm a beginner in labVIEW FPGA):
- In this Compact RIO (9075) I have 5 DMAs buss between the Host (Real Time controller) and the target (FPGA). The first one is set from "Host to Target- DMA" (let's call it DMA1) and the other 4 is from "Target to Host-DMA". In my Target application I have four separate parallel loops that itch of then is sending different data to the host. My question is how can I set the compiler for etch loop to use DMA2 for loop 1, DMA3 for loop 2, DMA4 for loop 3 and DMA5 for loop 4? Is it by different names? How does he know to use different DMA for etch loop? In addition, Is it possible to write and read to etch DMA at the same time (etch from different parallel loop).
- My second question is related to the previous question, what will I do if I'll having let's say, 10 different (loop instead of 4, again, unrelated)? I only have 4 DMA's left…? Can I use 10 different names (Buffer Items) somehow to all 4 DMA's
- I know that for same target the DMA bus is configure to transferring unsigned, 32-bit (U32). In this cRIO, I think I can configure the DMA data type to let's say U8 (for example). My question is if I configure it to U8 do I utility the bus for the maximum rate or should I packed the U8 to U16 using the Join and Split function block? What is the more efficient way to transferring date?
Thanks a lot,
Idan